This invention relates to apparatus for sectioning demountable semiconductor samples, particularly thin-edged crystal ribbon samples.
The need for sectioning or edge-polishing extremely thin semiconductor samples and the like has become increasingly important in modern technology applications. The need for such polishing arises since semiconductor wafers which are either sawn or mechanically polished, possess surface stresses (damage) which must be removed prior to semiconductor device fabrication. The extent of damage to the semiconductor's surface depends on the type of saw (e.g. whether the saw is of the wheel or the wire type) and the polishing conditions (e.g. grit material, bit size, and pad material). At times, the depth of the damaged region requires extensive working of the damaged surface, thereby subjecting the crystal sample to protracted periods of mechanical stresses.
Polycrystalline silicon solar cell devices require damage-free polishing in their fabrication. Although cells of about ten percent efficiency can be fabricated on conventionally prepared polycrystalline silicon substrates, it is expected that higher efficiencies can be obtained if performance-limiting grain-boundary effects are better understood and thereby rendered subject to moderation. Much of the investigative work to study photovoltaic mechanisms at grain boundaries involves electro-optical techniques. For this purpose, it is necessary to polish the surface of a polycrystalline silicon sample such that surface damage and profile variations, particularly those occurring at the grain boundaries, is minimized.
Several problems associated with conventional processing of polycrystalline silicon will be described briefly. Chemical and (fine grit) mechanical polishing techniques are known to result in steps at the grain boundaries due to different removal rates for various grain orientations, thereby subjecting the sample to a certain amount of defect structure. Also, mechanical polishing inherently causes surface damage and resultant high surface recombination velocity which degrades solar cell performance and complicates the interpretation of measurement data. Further, chemical polishing/etching usually causes "grooving" at the grain boundaries since the etch rate at grain boundaries is often higher than that of the grains themselves.
Analysis of defect and grain structure in semiconductor samples often involves sectioning a thin semiconductor sample. Typically, a desirable sectioning of a thin sample would allow convenient sample demounting, would provide damage-free polishing, and would eliminate chipping of the edge under investigation, i.e. the sectioning would provide excellent edge quality. A commonly used procedure for sectioning semiconductor samples consists of mounting the sample in epoxy, followed by lapping and grit polishing. Several variations in sample mounting and polishing are currently in use, depending on the types of semiconductor and polishing materials, and the nature of the analysis to be carried out. For example, several different types of epoxies are available which possess different degrees of chemical inertness relative to the sample. This presents the possibility of chemically softening the cured epoxy for sample demounting, but also gives rise to the possibility of chemical reaction of the sample. These difficulties are more fully explained in the article by B. L. Sopori, inventor of the present invention, T. Nilsson, and M. McClure, 128, Journal of the Electrochemical Society, 215 (1981).
Conventional sectioning procedures present several difficulties which will now be considered. Mechanical polishing leaves on the surface of the sample a residual damage which may interfere with structural details revealed by defect etching. Grit polishing results in poor edge quality in which chipping of the sectioned edge is frequently unacceptable. While chemical/mechanical polishing might be looked to as a successful alternative to remove the surface damage, such techniques might not be compatible with the epoxy molding method of mounting since even a small amount of dissolved epoxy which is spread over a sectioning surface will cause nonuniform etching. Further, large samples such as those of the polycrystalline type, crack under the stresses imparted to the sample during curing of the epoxy mounting material. Also, chemical solutions used for softening the cured epoxy mounting medium may react with the sample, thereby destroying the edge surface.
It is therefore an object of the present invention to provide an apparatus for sectioning thin samples, wherein the sample is easily demounted after polishing.
It is another object of the present invention to provide a sectioning apparatus which results in a damage-free polished product.
It is yet another object of the present invention to provide an apparatus for sectioning which eliminates chipping of the polished edge.
It is a further object of the present invention to provide an apparatus for sectioning of large samples, such as those of polycrystalline type, which eliminates stresses, particularly torsional stresses applied to the sample during mounting and demounting, as well as the polishing process itself.
It is another object of the present invention to provide an apparatus for sectioning of samples which avoids the use of chemical solutions, thereby eliminating any possible chemical reaction with the sample.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.